1. Field of the Invention
The present invention relates to a digital signal processor (hereinafter, referred to as a DSP).
2. Description of the Related Art
There has been well known an audio signal processing apparatus for executing signal processes for a sound field control to audio signals so as to give presence in a home or vehicle by producing a sound field which is obtained by simultaing the sound field in an acoustic space of a concert hall or a theater. For instance, such an apparatus has been disclosed in JP-A-64-72615. Such an audio signal processing apparatus has a DSP to execute a sound field control by digital operation processing the audio signals which were output from an audio signal source such as a tuner or the like. The DSP has: an operating section to execute operating processes such as four arithmetical operations or the like; and memories such as data RAM to store digital audio signal data to be supplied to the operating section, a coefficient RAM to store digital coefficient signal data (hereinafter, simply referred to as coeficient data) which is multiplied to the audio signal data, and the like. In the DSP, the signal data is transferred among the memories and from the memories to the operating section and operating processes of the signal data can be repetitively executed at a high speed in accordance with predetermined programs. On the other hand, the programs have been written in a writable program memory such as an RAM or the like in the DSP. Each time a sound field mode is switched by a switching operation, the program is changed by a microcomputer provided on the outside of the DSP. That is, every acoustic space can be produced by changing the program.
As shown in FIG. 1, the conventional DSP comprises buffer memories 1 and 2, a multiplier 3, an ALU 4, and an accumulator 5. On the other hand, the DSP also has a signal data RAM 6 to store input digital signal data and a coefficient data RAM 7 to store a plurality of coefficient data. Upon operation, the signal data is read out of the signal data RAM 6 and is supplied and held into the buffer memory 1 through a bus 8. The coefficient data is sequentially read out of the coefficient data RAM 7 at predetermined timings and suupplied and held into the buffer memory 2. Values which are indicated by the data held in the buffer memories 1 and 2 are multiplied by the multiplier 3. The result of the multiplication by the multiplier 3 is added to a value held in the accumulator 5 by the ALU 4 and the resultant addition data is held in the accumulator 5. The ALU 4 and accumulator 5 form accumulating means. The output terminal of the accumulator 5 is connected to the buffer memory 1 and the signal data RAM 6 through the bus 8 and therefore the data held in the accumulator 5 is transferred to the buffer memory 1 or the signal data RAM 6 via the bus 8.
There is a case where an arithmetic operation ##EQU1## in which two coefficient data values are multiplied to the signal data value and the multiplication results are accumulated is performed by using such a conventional DSP. a.sub.n denotes a coefficient which changes in accordance with the progress of the program. b.sub.n indicates a fixed coefficient. In this case, a.sub.1 .multidot.x.sub.1 is first calculated by the multiplier 3. The result of the calculation a.sub.1 .multidot.x.sub.1 is transferred to the buffer memory 1 via the ALU 4, accumulator 5, and bus 8 and a.sub.1 .multidot.x.sub.1 .multidot.b.sub.1 is calculated by the multiplier 3. At this time, the ALU 4 executes an operation such that 0 is added to the result of the multiplication by the multiplier 3. The calculated result a.sub.1 .multidot.b.sub.1 .multidot.x.sub.1 is held in the accumulator 5. Then, a.sub.2 .multidot.x.sub.2 is calculated by the multiplier 3. The calculated result a.sub.2 .multidot.x.sub.2 is transferred to the buffer memoroy 1 via the ALU 4, accumulator 5, and bus 8. a.sub.2 .multidot.x.sub.2 .multidot.b.sub.2 is calculated by the multiplier 3. The value of a.sub.1 .multidot.b.sub.1 .multidot.x.sub.1 held in the accumulator 5 and the value of the calculated a.sub.2 .multidot.b.sub.2 .multidot.x.sub.2 are added by the ALU 4 and the addition result is held in the accumulator 5. By repeating the above operations, ##EQU2## is calculated.
However, in such a conventional DSP, in the case of the arithmetic operation such as ##EQU3## in which a plurality of coefficients are multiplied to the signal data value, there are problems such that the number of steps of the program is large and it takes a long processing time.
On the other hand, there is a case where it is desired to calculate an approximate value in the DSP by using, for instance, ##EQU4## as an approximate equation of a non-linear functon. C.sub.n denotes coefficient data and x indicates signal data. However, such DSP in which only the coefficient data is supplied to the buffer memory 2 as shown in FIG. 1, cannot calculate the power of the signal data value x by the multiplier 3 and cannot obviously calculate ##EQU5##
The approximate value can be calculated by constructing in such a manner that the buffer memory 2 is connected to the bus 8 and the signal data from the signal data RAM 6 is supplied to the buffer memories 1 and 2 and the power of the signal data value x can be calculated by the multiplier 3.
However, it is necessary to hold the result of the calculation by the multiplier 3 into the accumulator and to transfer to the buffer memory 1 or 2 through the bus 8. For instance, to calculate c.sub.2 .multidot.x.sup.2, after x.sup.2 was multiplied by the multiplier 3, the value of the multiplication result is supplied and held into the accumulataor 5 via the ALU 4 and transferred to the buffer memory 1 through the bus 8 and, thereafter, c.sub.2 and x.sup.2 are multiplied. Therefore, new multiplication and accumulation cannot be performed until the data is transferred and there are problems such that the number of steps of the program increases and it takes a long processing time.